NXP Semiconductors
data output
by transmitter
data output
by receiver
PCA85132
LCD driver for low multiplex rates
not acknowledge
acknowledge
SCL from
master
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
mbc602
Fig 20. Acknowledgement on the I 2 C-bus
8.4 I 2 C-bus controller
The PCA85132 acts as an I 2 C-bus slave receiver. It does not initiate I 2 C-bus transfers or
transmit data to an I 2 C-bus master receiver. The only data output from the PCA85132 is
the acknowledge signal. Device selection depends on the I 2 C-bus slave address, on the
transferred command data, and on the hardware subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally tied
to V SS which defines the hardware subaddress 0. In multiple device applications
A0 and A1 are tied to V SS or V DD in accordance with a binary coding scheme. No two
devices with a common I 2 C-bus slave address must have the same hardware
subaddress.
8.5 Input filters
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6 I 2 C-bus protocol
Two I 2 C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA85132.
The entire I 2 C-bus slave address byte is shown in Table 18 .
Table 18.
I 2 C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
0
1
1
1
0
0
SA0
R/W
The PCA85132 is a write-only device and does not respond to a read access, therefore
bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCA85132 responds
to, is defined by the level tied to its SA0 input (V SS for logic 0 and V DD for logic 1).
PCA85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 July 2013
? NXP B.V. 2013. All rights reserved.
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